简介:Lowpoweraddercircuits,SERF,10T-Ⅰ,10T-Ⅱ,10T-Ⅲandacomplementaryadder(28T)atphysicallayoutlevelareevaluated.Simulationsbasedontheextractedaddercircuitlayoutsareruntoassesshowvariouscircuitsetupscanimpactthespeedandpowerconsumption.Inaddition,impactsofoutputinvertersonthecircuitperformanceofmodifiedSERFand10Taddersduetothresholdlossproblemarealsoexamined.Differencesamongtheseaddersareaddressedandapplicationsoftheseaddersaresuggested.
简介:Adoublephotodiode(PD)constructedbyp?/NwelljunctionandN-well/p-subjunctionwasdesignedandfabricatedinaUMC0.18-lmCMOSprocess.BasedonthedevicestructureandmechanismofdoublePD,anovelsmall-signalequivalentcircuitmodelconsideringthecarriertransiteffectandtheparasiticRCtimeconstantwaspresented.Bythismodelwithcompleteelectroniccomponents,thedoublePDcanbeincorporatedinacommercialcircuitsimulator.ThecomponentvalueswereextractedbyfittingthemeasuredS-parametersusingsimulatedannealingalgorithm,andagoodagreementbetweenthemeasurementandthesimulationresultswasachieved.
简介:A0.18lmCMOSlownoiseamplifier(LNA)byutilizingnoise-cancelingtechniquewasdesignedandimplementedinthispaper.Current-reuseandself-biastechniqueswereusedinthefirststagetoachieveinputmatchingandreducepowerconsumption.ThecoresizeoftheproposedCMOSLNAcircuitwithoutinductorwasonly128lm9226lm.ThemeasuredpowergainandnoisefigureoftheproposedLNAwere20.6and1.9dB,respectively.The3-dBbandwidthcoversfrequencyfrom0.1to1.2GHz.Whenthechipwasoperatedatasupplyvoltageof1.8V,itconsumed25.69mW.ThehighperformanceoftheproposedLNAmakesitsuitableformultistandardlow-costreceiverfront-endswithintheabovefrequencyrange.
简介:有非线性赔偿的一个高速度列平行CDS/ADC电路在这份报纸被建议。相关双采样(CDS)和analog-to-digital变换器(模数转换器)工作基于二漂浮门inverters和开关电容器网络集成于一个三阶段的列平行电路。传统的单个斜坡的模数转换器的变换率被划分量子化到粗糙的步和好步加快。一个存储电容器被用来存储粗糙的步的结果并且定位好步的斜面信号的节,它能从2n把钟步骤归结为2(n/2+1)。漂浮的门inverters被实现减少电源消费。它的导致的非线性的偏移量被把一个赔偿模块介绍给inverter的输入取消,它能在建议电路的三个阶段使相等联合路径。这个电路与640为互补金属氧化物半导体图象传感器被设计并且模仿,
简介:对T型衰减器的插入损耗和衰减性能进行了理论分析,在此基础上设计了一个用于跳时超宽带(TH-UWB)通信的载波频率为4GHz的通断键控(OOK)调制器.该调制器的核心是一个T型RFCMOS衰减器,其电路拓扑结构包括3个主要部分:振荡频率为4GHz的振荡器、由射频CMOS晶体管构成的T型衰减器和带有L型结构的输出阻抗匹配网络.该调制器由一个脉位调制(PPM)信号控制,使已调信号的包络随控制信号的幅度而变化,以实现调制功能.除此之外,输出匹配网络将调制器的输出阻抗匹配到50Ω负载.调制器采用0.18μm射频CMOS工艺进行设计并仿真,其芯片经过测试,在1.8V电源和50Ω负载下有65mV的输出幅度,输出端回波损耗(S11)小于-10dB,功耗为12.3mW,芯片尺寸为0.7mm×0.8mm.